Progress of capacity enlargement of a dynamic random access memory (DRAM) is significant. Particularly, recently, a layered DRAM in which a plurality of memory chips are stacked is suggested, and capacity enlargement is in progress. A layered semiconductor device in which a plurality of semiconductor chips are stacked can improve the degree of integration per area of the semiconductor device, and is widely used without limitation to the DRAM.
In the layered semiconductor device in which a plurality of semiconductor chips (for example, memory chips) are stacked as described above, a ThruChip interface (TCI) technology is known as a data transmission and reception method between semiconductor chips. The TCI technology is a general name of a technology of performing communication between semiconductor chips in a contactless manner. For example, a coil is provided each of the semiconductor chips, and data transmission between the semiconductor chips can be performed by magnetic field coupling between coils.
Hereinafter, as the TCI technology, description will be given of an example in which magnetic field coupling using a coil is used. FIG. 8 illustrates a configuration view illustrating a circuit configuration in which data transmission between semiconductor chips is performed by using the conventional TCI technology Here, a communication technology for carrying out data transmission between semiconductor chips is referred to as inter-substrate communication.
In FIG. 8, a transmission side represents a configuration on a semiconductor chip on a data transmission side, and a reception side represents a configuration on another semiconductor chip on a data reception side. In FIG. 8, a transmission side and a reception side which correspond to one piece of data DI are illustrated. The data DI stated here is data on one digital data line, and can take a value of “1” or
In FIG. 8, the data DI is input to a non-inverting transmission amplifier 200 and an inverting transmission amplifier 202. A transmission coil 204 is connected between an output terminal of the non-inverting transmission amplifier 200 and an output terminal of the inverting transmission amplifier 202. Due to the connection, in a case where the data D1 is “1”, a positive-phase voltage is applied to the transmission coil 204, and a positive-phase magnetic field is generated. Here, it is assumed that the positive-phase magnetic field represents a magnetic field in a direction indicated by an arrow in FIG. 8. On the other hand, in a case where the data D1 is “0”, a reversed-phase voltage is applied to the transmission coil 204, and a reversed-phase magnetic field is generated. It is assumed that the reversed-phase magnetic field represents a magnetic field in a direction opposite to the arrow illustrated in FIG. 8.
In addition, transmission CLK that is a transmission clock signal is applied to the non-inverting transmission amplifier 200 and the inverting transmission amplifier 202, and each of the amplifiers operates only in a case where the transmission CLK is “1”. In addition, in a case where the transmission CLK is “0”, the output terminals of the respective amplifiers enter a “0” or high-impedance state in combination, a current does not flow to the transmission coil, and a magnetic field is not generated. As described above, the transmission side (semiconductor chip thereof) includes the non-inverting transmission amplifier 200, the inverting transmission amplifier 202, and the transmission coil 204.
In FIG. 8, when a current flows to the transmission coil 204 on the transmission side, the same current VR (in an opposite direction) also flows to a reception coil 206 due to magnetic field coupling (electromagnetic induction). In principle, the current VR is a current that is equivalent to the current that flows to the transmission coil 204 on the transmission side, and is a current with the same magnitude.
The current VR that flows to the reception coil 206 is input to the sense amplifier 208. An amplification rate of the sense amplifier 208 is set to a sufficiently large value, and an output signal thereof becomes a digital signal of “1” or “0” in correspondence with a direction of the current VR. A flip-flop 210 latches the output signal of the sense amplifier 208 in synchronization with a reception CLK that is a reception clock, and outputs the latched signal to a data line DO that outputs received data. As described above, the reception side (semiconductor chip thereof) includes the reception coil 206, the sense amplifier 208, and the flip-flop 210. According to the above-described configuration, data (data to be transmitted) of a data line DI on the transmission side is transmitted to the reception side through inter-substrate transmission using the transmission coil 204 and the reception coil 206, and is output from the data line DO.
Description by Time Chart
A time chart of a signal on the transmission side and the reception side in FIG. 8 is illustrated in FIG. 9. In FIG. 9, DI represents data that is a signal on the data line DI and data to be transmitted. In FIG. 9, the transmission CLK represents a transmission clock, and VR is a current value of the reception coil 206 and is substantially equivalent to a voltage of the reception coil 206. In addition, the VR is substantially equivalent to a current and a voltage of the transmission coil 204. In addition, in FIG. 9, DO represents data that is received on the reception side, and represents data on the data line DO. In addition, in FIG. 9, it is assumed that time passes from the left to the right.
First. In a state in which the DI is “1”, one pulse occurs in the transmission CLK, a current in a direction corresponding to the state of DI flows to the transmission coil 204 during the one pulse. A current that is substantially the same as the current is indicated by VR in FIG. 9. In the example of FIG. 9, when the transmission CLK appears by one clock in a state in which the DI is “1”, it enters a state in which the VR flows in a positive direction in correspondence with the appearance.
On the reception side, the VR that appears in the reception coil 206 is amplified by the sense amplifier 208. In a case where the VR is equal to or greater than a predetermined threshold value, a signal that becomes “1” is output, and in a case where the VR is less than the threshold value, a signal that becomes “0” is output. As illustrated in FIG. 9, the reception CLK is a clock of which rising is slightly delayed in comparison to the one pulse of the transmission CLK. On the reception side, at the rising of the reception CLK, the flip-flop 210 latches an output signal of the sense amplifier 208, and outputs the latched signal as DO. The example of FIG. 9 illustrates a state in which in a case where the DI is “1”, at the rising of the reception CLK, the DO varies to “1”.
In FIG. 9, a case where the DI is “0” is also illustrated as in a case where the DI is “1”. In a case where the DI is “0”, as illustrated in FIG. 9, a current direction of the VR is a negative direction. As a result, an output signal of the sense amplifier 208 becomes “0”, and thus the flip-flop 210 latches “0”, and the DO becomes “0”. As described above, data that is output from the transmission side is received on the reception side.
Here, the transmission CLK is transmitted from the transmission side to the reception side by using an additional TCI technology and the like, and is used on the reception side as the reception CLK. As a result, as illustrated in FIG. 9, the reception CLK becomes a clock that is slightly delayed in comparison to the transmission CLK.
The clock signal is transmitted from a semiconductor chip on the transmission side, from which data is transmitted, to a semiconductor chip on the reception side that receives data by the TCI technology. A view illustrating this state is shown in FIG. 4. FIG. 4 is a view illustrating a stacking example of semiconductor chips of a layered semiconductor storage device, and a state in which a coil is provided on each of the semiconductor chips, and a clock signal is transmitted by a magnetic field coupling using the coil.
FIG. 4(a) illustrates a state in which the transmission CLK is transmitted from an active interposer A-I/P to other semiconductor chips (memory chips DRAM0 to DRAM7, and DRAMR). In addition, in contrast, FIG. 4(b) illustrates a state in which the transmission CLK is transmitted from the memory chips DRAM to the active interposer A-I/P. A configuration related to FIG. 4 will be described again later.